One trend in modern integrated circuit manufacture is to produce semiconductor devices, such as field effect transistors (FETs), which are as small as possible. In a typical FET, a source and a drain are formed in an active region of a semiconductor substrate by implanting n-type or p-type impurities in the semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
Although the fabrication of smaller transistors allows more transistors to be placed on a single substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. In addition, achieving a desired device dimension is often difficult as device designers are constrained by limitations imposed by various manufacturing techniques. For example, photolithography is often used to pattern a mask layer that is used to determine the size and placement of device components, such as the gate. However, lithographic limits restrict gate formation to a certain minimum length.
Asymmetric FET devices provide some benefits over conventional FET devices including, for example, improved device performance and reduced drain impact ionization. Although asymmetric FET devices provide an improvement over conventional FETs, the scaling of prior art asymmetric FET devices is also restricted since lithography is also used to define the length of the gate.
Accordingly, there exists a need in the art for semiconductor devices, such as asymmetric FETs, that have a reduced scale and improved device performance. In addition, a need exists for fabrication techniques for making those semiconductor devices.